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SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 1 post office box 655303 ? dallas, texas 75265 9 channels for the data and control paths of the small computer systems interface (scsi) supports single-ended and low-voltage differential (lvd) scsi cmos input levels ('lvdm976) or ttl input levels ('lvdm977) available includes diffsens comparators on cde0 single-ended receivers include noise pulse rejection circuitry packaged in thin shrink small-outline package with 20-mil terminal pitch low disabled supply current 7 ma maximum power-up/down glitch protection bus is high-impedance with v cc = 1.5 v pin-compatible with the sn75976adgg high-voltage differential transceiver description the SN75LVDM976 and sn75lvdm977 have nine transceivers for transmitting or receiving the signals to or from a scsi data bus. they offer electrical compatibility to both the single-ended signaling of x3.277:1996scsi3 parallel inter- face (fast20) and the new low-voltage differen- tial signaling method of proposed standard 1142d scsi parallel interface 2 (spi2). the differential drivers are nonsymmetrical. the scsi bus uses a dc bias on the line to allow terminated fail safe and wired-or signaling. this bias can be as high as 125 mv and induces a difference in the high-to-low and low-to-high transition times of a symmetrical driver. in order to reduce pulse skew, an lvd scsi driver's output characteristics become nonsymmetrical. in other words, there is more assertion current than negation current to or from the driver. this allows the actual differential signal voltage on the bus to be symmetrical about 0 v. even though the driver output characteristics are nonsymmetrical, the design of the 'lvdm976 drivers maintains balanced signaling. balanced means that the current that flows in each signal line is nearly equal but opposite in direction and is one of the keys to the low-noise performance of a differential bus. available options package t a tssop (dgg) cmos input levels tssop (dgg) ttl inputs levels 0 c to 70 c SN75LVDM976dgg SN75LVDM976dggr 2 sn75lvdm977dgg sn75lvdm977dggr 2 2 the r suffix designates a taped and reeled package. copyright ? 2000, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. dgg package (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 inv/non gnd gnd 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re v cc gnd gnd gnd gnd gnd v cc 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re cde2 cde1 cde0 9b+ 9b 8b+ 8b 7b+ 7b 6b+ 6b v cc gnd gnd gnd gnd gnd v cc 5b+ 5b 4b+ 4b 3b+ 3b 2b+ 2b 1b+ 1b
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 2 post office box 655303 ? dallas, texas 75265 description (continued) the signal symmetry requirements of the lvd-scsi bus mean you can no longer obtain logical inversion of a signal by simply reversing the differential signal connections. this requires the ability to invert the logic convention through the inv/non terminal. this input would be a low for scsi controllers with active-high data and high for active-low data. in either case, the b+ signals of the transceiver must be connected to the signal+ line of the scsi bus and the b of the transceiver to the signal line. the cde0 input incorporates a window comparator to detect the status of the diffsens line of a scsi bus. this line is below 0.5 v, if using single-ended signals, between 1.7 v and 1.9 v if low-voltage differential, and between 2.4 v and 5.5 v if high-voltage differential. the outputs assume the characteristics of single-ended or lvd accordingly or place the outputs into high-impedance, when hvd is detected. this, and the inv/non input, are the only differences to the trade-standard function of the sn75976a hvd transceiver. two options are offered to minimize the signal noise margins on the interface between the communications controller and the transceiver. the SN75LVDM976 has logic input voltage thresholds of about 0.5 v cc . the sn75lvdm977 has a fixed logic input voltage threshold of about 1.5 v. the input voltage threshold should be selected to be near the middle of the output voltage swing of the corresponding driver circuit. the SN75LVDM976 and sn75lvdm977 are characterized for operation over an free-air temperature range of t a = 0 c to 70 c.
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 3 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) 1b 2b 2b + 3b 3b + 4b 4b + channel 4 channel 3 channel 2 4de/re 4a 3de/re 3a 2de/re 2a 1de/re 1a cde1 cde0 + + 1b + inv/non 5b 5b + 6b 6b + 7b 7b + channel 7 channel 6 channel 5 7de/re 7a 6de/re 6a 5de/re 5a 8b 8b + channel 8 8de/re 8a 2.4 v (internal) 0.5 v (internal) cde2 9b 9de/re 9a 9b + 1deb 1dea 1reb 1rea se lvd se lvd se lvd inv/non inv/non 9deb 9dea 9reb 9rea 1deb 1reb 1dea 1rea 9deb 9reb 9dea 9rea a b
b b+ a de/re v id figure 1. inverting lvd transceiver b b+ a de/re figure 2. inverting single-ended transceiver b b+ a figure 3. inverting single-ended driver b b+ a figure 4. inverting lvd driver SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 4 post office box 655303 ? dallas, texas 75265 logic diagrams and function tables function table inputs outputs (b+ b) de/re a b+ b a v id 30 mv l na z z l 30 mv < v id < 30 mv l na z z ? v id 30 mv l na z z h open circuit l na z z ? na h l h l z na h h l h z function table inputs outputs b de/re a b+ b a h l na l z l l l na l z h open circuit l na l z ? na h l l h z na h h l l z function table input outputs a b+ b l l h h l l function table input outputs a b+ b l h l h l h
b b+ a figure 5. noninverting lvd driver b b+ a de/re v id figure 6. noninverting lvd transceiver b b+ a de/re figure 7. noninverting single-ended transceiver b b+ a figure 8. noninverting single-ended driver SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 5 post office box 655303 ? dallas, texas 75265 logic diagrams and function tables (continued) function table input outputs a b+ b l l h h h l function table inputs outputs (b+ b ) de/re a b+ b a v id 30 mv l na z z h 30 mv < v id < 30 mv l na z z ? v id 30 mv l na z z l open circuit l na z z ? na h l l h z na h h h l z function table inputs outputs b de/re a b+ b a h l na l z h l l na l z l open circuit l na l z ? na h l l l z na h h l h z function table input outputs a b+ b l l l h l h
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 6 post office box 655303 ? dallas, texas 75265 1b 1b+ 1a 1de/re 2b 2b+ 2a 2de/re 3b 3b+ 3a 3de/re 4b 4b+ 4a 4de/re 5b 5b+ 5a 5de/re 6b 6b+ 6a 6de/re 7b 7b+ 7a 7de/re 8b 8b+ 8a 8de/re 9b 9b+ 9a 9de/re control inputs cde0 0.7 v < v i < 1.9 v inv/non l cde1 l cde2 l (a) 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 6a 7a 8a 9a 9de/re control inputs cde0 0.7 v < v i < 1.9 v inv/non l cde1 l cde2 h 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ (b) 1a 2a 3a 4a 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re control inputs cde0 0.7 v < v i < 1.9 v inv/non l cde1 h cde2 l 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ (c) figure 9. logic diagrams
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 7 post office box 655303 ? dallas, texas 75265 1a 2a 3a 4a 5a 6a 7a 8a 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ control inputs cde0 0.7 v < v i < 1.9 v inv/non l cde1 h cde2 h (a) 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ control inputs cde0 0.7 v < v i < 1.9 v inv/non h cde1 l cde2 l (b) 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 6a 7a 8a 9a 9de/re control inputs cde0 0.7 v < v i < 1.9 v inv/non h cde1 l cde2 h (c) 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ figure 10. logic diagrams
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 8 post office box 655303 ? dallas, texas 75265 1a 2a 3a 4a 5a 6a 7a 8a 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ control inputs cde0 0.7 v < v i < 1.9 v inv/non h cde1 h cde2 h (a) 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ control inputs cde0 v i < 0.5 v inv/non l cde1 l cde2 l (b) 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 6a 7a 8a 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ control inputs cde0 v i < 0.5 v inv/non l cde1 l cde2 h (c) figure 11. logic diagrams
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 9 post office box 655303 ? dallas, texas 75265 1a 2a 3a 4a 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ control inputs cde0 v i < 0.5 v inv/non l cde1 h cde2 l (a) control inputs cde0 v i < 0.5 v inv/non l cde1 h cde2 h (b) 1a 2a 3a 4a 5a 6a 7a 8a 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ control inputs cde0 v i < 0.5 v inv/non h cde1 l cde2 l (c) 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ figure 12. logic diagrams
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 10 post office box 655303 ? dallas, texas 75265 control inputs cde0 v i < 0.5 v inv/non h cde1 l cde2 h (a) 1a 1de/re 2a 2de/re 3a 3de/re 4a 4de/re 5a 6a 7a 8a 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ 1a 2a 3a 4a 5a 5de/re 6a 6de/re 7a 7de/re 8a 8de/re 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ control inputs cde0 v i < 0.5 v inv/non h cde1 h cde2 l (b) 1a 2a 3a 4a 5a 6a 7a 8a 9a 9de/re 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ control inputs cde0 v i < 0.5 v inv/non h cde1 h cde2 h (b) figure 13. logic diagrams
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 11 post office box 655303 ? dallas, texas 75265 control inputs cde0 v i > 2.5 v inv/non x cde1 x cde2 x 1a 2a 3a 4a 5a 6a 7a 8a 9a 1b 1b+ 2b 2b+ 3b 3b+ 4b 4b+ 5b 5b+ 6b 6b+ 7b 7b+ 8b 8b+ 9b 9b+ high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z high z figure 14. logic diagrams
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 12 post office box 655303 ? dallas, texas 75265 input and output equivalent schematic diagrams v cc input 10ua v cc input 10ua cde1, cde2, de/re inputs a and inv/non inputs i ref 37 w bn v cc i ref 113 w 15 w 113 w v cc i ref i ref v cc 113 w 37 w 15 w 15 w bp b+ input b input v cc a output a v cc input cde0 input
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 13 post office box 655303 ? dallas, texas 75265 terminal functions terminal 'lvdm976 logic 'lvdm977 logic i/o termination description name no. l og i c level l og i c level i/o termination description 1a 9a 4,6,8,10, 19,21,23, 25,27 cmos ttl i/o pullup 1a 9a carry data to and from the communication controller. 1b 9b 29,31,33, 35,37,46, 48,50,52 lvd or ttl lvd or ttl i/o none 1b to 9b are the signals to and from the data bus. when inv/non is low, the logic sense is the opposite that of the a input (inverted). when inv/non is high, the logic sense is the same as the a input (noninverted). 1b + 9b + 30,32,34, 36,38,47, 49,51,53 lvd or gnd lvd or gnd i/o none when in the lvd mode, 1b+ 9b+ are signals to or from the data bus and follow the same logic sense as the a input when inv/non is low (noninverted). the logic sense is opposite that of the a input (inverted) when inv/non is high. when in single-ended mode, these terminals become a ground connection through a transistor and do not switch. cde0 54 trinary trinary input none cde0 is the common driver enable 0. with the driver enabled and the cde0 input less than 0.5 v, the driver output is single-ended mode. with the driver enabled and the cde0 input between 0.7 v and 1.9 v the driver output is lvd mode. all drivers are disabled when the input is greater than 2.4 v. cde1 55 cmos ttl input pulldown cde1 is the common driver enable 1. when cde1 is high, drivers 1 4 are enabled cde2 56 cmos ttl input pulldown cde2 is the common driver enable 2. when cde2 is high, drivers 5 to 8 are enabled. 1de/re 9de/re 5,7,9,11, 20,22,24, 26,28 cmos ttl input pulldown 1de/re 9de/re are direction controls that transmit data to the bus when it is high and cde0 is below 2.2 v. data is received from the bus when 1de/re 9de/re, cde1, and cde2 are low. gnd 2,3,13,14, 15,16,17, 40,41,42, 43,44 na na power na gnd is the circuit ground. inv/non 1 cmos cmos input pullup a high-level input to inv/non inverts the logic to and from the a terminals. (i.e., the voltage at a terminal and the corresponding b terminal are in phase.) v cc 12,18,39, 45 na na power na supply voltage
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 14 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature (unless otherwise noted) 2 supply voltage range, v cc (see note 1) 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (a, inv/non ) 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (de/re , b+, b, cde0, cde1, cde2) 0.5 v to 5.25 v . . . . . . . . . . . . . . . . . . . . . . . . continuous total power dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note 1: all voltage values are with respect to gnd unless otherwise noted. dissipation rating table package t a 25 c power rating derating factor above t a = 25 c t a = 70 c power rating dgg 978 mw 10.8 mw/ c 492 mw recommended operating conditions (see figure 15) min nom max unit supply voltage, v cc 4.75 5 5.25 v high level in p ut voltage v ih SN75LVDM976 0.7 v cc v high - le v el inp u t v oltage , v ih sn75lvdm977 2 v low level in p ut voltage v il SN75LVDM976 0.3 v cc v lo w- le v el inp u t v oltage , v il sn75lvdm977 0.8 v differential input voltage, |v id | differential receiver 0.03 3.6 v common-mode input voltage, v ic 0.7 1.8 v differential output voltage bias, v od(bias) differential 100 125 mv high level out p ut current i oh single-ended driver 7 ma high - le v el o u tp u t c u rrent , i oh receiver 2 ma low level out p ut current i ol single-ended driver 48 ma lo w- le v el o u tp u t c u rrent , i ol receiver 2 ma differential load impedance, z l 40 65 w operating free-air temperature, t a 0 70 c
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 15 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit i ih high level in p ut current cde1 and cde2 50 m a i ih high - le v el inp u t c u rrent inv/non 50 m a i il low level in p ut current cde1 and cde2 50 m a i il lo w- le v el inp u t c u rrent inv/non 50 m a disabled 7 lvd drivers enabled, no load 26 i cc supply current single-ended drivers enabled, no load 10 ma lvd receivers enabled, no load 26 singled-ended receivers enabled, no load 7 c i input capacitance bus terminal v i = 0.2 sin (2 p (1e06)t) + 0.5 0.01 v 9.5 p f d c i difference in input capacitance between b+ and b 0.2 f 2 all typical values are at v cc = 5 v, t a = 25 c. diffsens (cde0) receiver electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit v it1 input threshold voltage 0.5 0.6 0.7 v v it2 input threshold voltage 1.9 2.1 2.4 v i i input current 0 v v i 2.7 v 1 m a i i(off) power-off input current v cc = 0, 0 v v i 2.7 v 1 m a 2 all typical values are at v cc = 5 v, t a = 25 c.
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 16 post office box 655303 ? dallas, texas 75265 lvd driver electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions min typ 2 max unit v i(1) = 0.96 v, v i(2) = 0.53 v, 270 460 780 v od(h) driver differential high-level out- i(1) , i(2) , see figure 16 0.69|v od(l) |+ 50 1.45|v od(l) | 65 mv v od(h) g put voltage v i(1) = 1.96 v, v i(2) = 1.53 v, 270 500 780 mv i(1) , i(2) , see figure 16 0.69|v od(l) |+ 50 1.45|v od(l) | 65 v od(l) driver differential low-level output v i(1) = 0.96 v, v i(2) = 0.53 v, see figure 16 260 400 640 mv v od(l) voltage v i(1) = 1.96 v, v i(2) = 1.53 v, see figure 16 260 400 640 mv v oc(ss) steady-state common-mode out- put voltage 1.1 1.2 1.5 v d v oc(ss) change in steady-state common- mode output voltage between logic states v i(1) = 1.41 v, v i(2) = 0.99 v, see figure 17 50 120 mv v oc(pp) peak-to-peak common-mode output voltage 80 150 mv i ih high level in p ut current a v ih = 3.3 v ('976) 7 m a i ih high - le v el inp u t c u rrent de/re ih () v ih = 2 v ('977) 50 m a i il low level in p ut current a v il = 1.6 v ('976) 30 m a i il lo w- le v el inp u t c u rrent de/re il () v il = 0.8 v ('977) 8 m a i o(off) power-off output current v cc = 0, 0 v v o 2.5 v 1 m a i os short-circuit output current 0 v v o 2.5 v 24 ma i oz high-impedance output current v o = 0 or 2.5 v 1 m a 2 all typical values are at v cc = 5 v, t a = 25 c. lvd driver switching characteristics over recommended operating conditions (unless otherwise noted) (see figure 16) parameter test conditions min typ 2 max unit t plh propagation delay time, low-to-high level output 2.9 8.8 ns t phl propagation delay time, high-to-low level output v5v v 1 41 v 2.9 8.8 ns t r differential output signal rise time v cc = 5 v, v i2 = 0 99 v v i1 = 1.41 v, t a =25 c 1 3 6 ns t f differential output signal fall time v i2 = 0 . 99 v , t a = 25 c 1 3 6 ns t sk(p) pulse skew (|t phl t plh |) 3.7 ns t sk(lim) skew limit 3 5.9 ns t phz propagation delay time, high-level to high-impedance output v i1 = 1.41 v, v i2 = 0.99 v, 50 ns t en enable time, receiver to driver i1 see figure 18 i2 33 ns 2 all typical values are at v cc = 5 v, t a = 25 c. 3 t sk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the s ame ambient temperature.
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 17 post office box 655303 ? dallas, texas 75265 single-ended driver electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit v oh high level out p ut voltage b out p ut i oh = 7 ma, see figure 19 2 3.24 v v oh high - le v el o u tp u t v oltage b o u tp u t i oh = 0 ma 3.7 v b output v cc = 5 v, i ol = 48 ma 0.5 v v ol low-level output voltage b+ i ol = 25 ma 0.5 v b + i ol = 25 ma 0.5 v i ih high level in p ut current a v ih = 3.3 v ('976), 7 m a i ih high - le v el inp u t c u rrent de/re ih (), v ih = 2 v ('977) 50 m a i il low level in p ut current a v il = 1.6 v ('976), 30 m a i il lo w- le v el inp u t c u rrent de/re il (), v il = 0.8 v ('977) 8 m a i o(off) power-off output current b v cc = 0, 0 v v o 5.25 v 1 m a i oz high-impedance output current v o = 0 or v cc 1 m a single-ended driver switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ 2 max unit t plh propagation delay time, low-to-high level output 2.7 8.2 ns t phl propagation delay time, high-to-low level output v cc = 5v, 2.7 8.2 ns t r differential output signal rise time v cc = 5 v , t a = 25 c, 0.5 4 ns t f differential output signal fall time see figure 19 0.5 4 ns t sk(p) pulse skew (|t phl t plh |) 3.4 ns t sk(lim) skew limit 3 5.5 ns t en enable time, receiver to driver see figure 20 50 ns t plz propagation delay time, low-level to high-impedance output see fig u re 20 30 ns 2 all typical values are at v cc = 5 v, t a = 25 c. 3 t sk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the s ame ambient temperature. lvd receiver electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit v it+ positive-going differential input voltage threshold see figure 21 30 mv v it negative-going differential input voltage threshold see fig u re 21 30 mv v oh high-level output voltage i oh = 2 ma 3.7 v v ol low-level output voltage i ol = 2 ma 0.5 v i i input current, b+ or b v i = 0 v to 2.5 v 1 m a i i(off) power-off input current, b+ or b v cc = 0, v i = 0 v to 2.5 v 1 m a i ih high-level input current, de/re v ih = 3.3 v ('976), v ih = 2 v ('977) 50 m a i il low-level input current, de/re v il = 1.6 v ('976), v il = 0.8 v ('977) 8 m a i oz high-impedance output current v o = 0 or v cc 30 m a
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 18 post office box 655303 ? dallas, texas 75265 lvd receiver switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ 2 max unit t plh propagation delay time, low-to-high level output 4.5 10 ns t phl propagation delay time, high-to-low level output v cc = 5v, 4.5 10 ns t sk(p) pulse skew (|t phl t plh |) v cc = 5 v , t a = 25 c, 3 ns t r output signal rise time see figure 21 8 ns t f output signal fall time 8 ns t sk(lim) skew limit 3 5.5 ns t phz propagation delay time, high-level to high-impedance output 42 ns t plz propagation delay time, low-level to high-impedance output see figure 18 20 ns t en enable time, driver to receiver 26 ns 2 all typical values are at v cc = 5 v, t a = 25 c. 3 t sk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the s ame ambient temperature. single-ended receiver electrical characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit v it+ positive-going input voltage threshold b 1.6 1.9 v v it negative-going input voltage threshold b 1 1.1 v v oh high-level output voltage i oh = 2 ma 3.7 4.6 v v ol low-level output voltage i ol = 2 ma 0.3 0.5 v i i input current b v i = 0 to v cc 1 m a i i(off) power-off input current b v cc = 0 v, v i = 0 to 5.25 v 1 m a i ih high-level input current de/re v ih = 3.3 v ('976), v ih = 2 v ('977) 50 m a i il low-level input current de/re v il = 1.6 v ('976), v il = 0.8 v ('977) 8 m a i oz high-impedance output current v o = 0 or v cc 30 m a single-ended receiver switching characteristics over recommended operating conditions (unless otherwise noted) parameter test conditions min typ max unit t plh propagation delay time, low-to-high level output 7 12.5 ns t phl propagation delay time, high-to-low level output v cc = 5v, 7 12.5 ns t sk(p) pulse skew (|t phl t plh |) v cc = 5 v , t a = 25 c, 3.5 ns t r output signal rise time see figure 22 8 ns t f output signal fall time 8 ns t sk(lim) skew limit 2 5.5 ns t phz propagation delay time, high-level to high-impedance output 20 ns t plz propagation delay time, low-level to high-impedance output see figure 20 30 ns t en enable time, driver to receiver 48 ns 2 t sk(lim) is the maximum delay time difference between any two drivers on any two devices operating at the same supply voltage and the s ame ambient temperature.
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 19 post office box 655303 ? dallas, texas 75265 parameter measurement information b b+ i i a v i i ob + i ob v od v ob v ob+ v oc v ob v ob 2 figure 15. voltage and current definitions t f t r t phl a de/re inv/non cde2 cde0 cde1 input 5 v 1.3 v open open 0 v or 5 v c l = 10 pf c l = 10 pf v od b+ b 75 w 100 w 100 w + + v2 v1 output input 0 v t plh solid line is inv/non at 0 v. dashed line is inv/non at 5 v. 0.7 v cc ('976) 2 v ('977) 0.3 v cc ('976) 0.8 v ('977) v od(h) v od(l) 100% 80% 20% 0% 50 w notes: a. all input pulses are supplied by a generator having the following characteristics: t r or t f < 1 ns, pulse repetition rate (prr) = 10 mpps, pulsewidth = 50 ns 5 ns, z o = 50 w . b. c l includes instrumentation and fixture capacitance within 0,06 m of the d.u.t. figure 16. differential output signal test circuit, timing, and voltage definitions
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 20 post office box 655303 ? dallas, texas 75265 parameter measurement information a de/re inv/non cde2 cde0 cde1 input 5 v 1.3 v open open 0 v or 5 v c l = 50 pf b+ b v2 v1 v oc(pp) 100 w 100 w 37.5 w 37.5 w v oc v oc(ss) input output 50 w 0.7 v cc ('976) 2 v ('977) 0.3 v cc ('976) 0.8 v ('977) notes: a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 10 mpps, pulsewidth = 50 ns 5 ns, z o = 50 w . b. c l includes instrumentation and fixture capacitance within 0,06 m of the d.u.t. c. the measurement of v oc(pp) is made on test equipment with a 3 db bandwidth of at least 300 mhz. figure 17. test circuit and definitions for the driver common-mode output voltage
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 21 post office box 655303 ? dallas, texas 75265 parameter measurement information a de/re inv/non cde2 cde0 cde1 v 1.3 v open open 0 v or 5 v b+ b v2 v1 100 w 100 w 37.5 w 37.5 w v od c l = 50 pf c l = 50 pf input c l = 50 pf input t en(d) 50% test circuit voltage waveforms t phz(d) 0 v 0.4 v 0.12 v v od t en(r) t en(d) 0.2 v 1.4 v 5 v v a t en(d) 50% t phz(d) 0 v 0.4 v 0.12 v t en(r) t en(d) 0.2 v 1.4 v 5 v v at 5 v, inv/non at 0 v v at 0 v, inv/non at 5 v 620 w 0.7 v cc ('976) 2 v ('977) 0.3 v cc ('976) 0.8 v ('977) 0.7 v cc ('976) 2 v ('977) 0.3 v cc ('976) 0.8 v ('977) notes: a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 1 mpps, pulsewidth = 500 ns 50 ns, z o = 50 w . b. c l includes instrumentation and fixture capacitance within 0,06 m of the d.u.t. figure 18. lvd transceiver enable and disable time test circuit and definitions
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 22 post office box 655303 ? dallas, texas 75265 parameter measurement information t f t r t phl a de/re inv/non cde2 cde0 cde1 input 0 v 0 v open open 0 v or 5 v c l = 10 pf v o b 47 w + output input 1.4 v t plh solid line is inv/non at a high-level input. dashed line is inv/non at a low-level input. 100% 80% 20% 0% i o 2.5 v 50 w 0.7 v cc ('976) 2 v ('977) 0.3 v cc ('976) 0.8 v ('977) notes: a. all input pulses are supplied by a generator having the following characteristics: t r or t f < 1 ns, pulse repetition rate (prr) = 10 mpps, pulsewidth = 50 ns 5 ns, z o = 50 w . b. c l includes instrumentation and fixture capacitance within 0,06 m of the d.u.t. figure 19. single-ended driver switching test circuit
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 23 post office box 655303 ? dallas, texas 75265 parameter measurement information v a a de/re inv/non cde2 cde0 cde1 v 0 v open open 0 v or 5 v b input c l = 50 pf t en(r) 50% test circuit voltage waveforms t plz(r) 0.5 v v a t en(d) t plz(d) v b t en(r) t phz(r) v and inv/non at 5 v v and inv/non at 0 v c l = 10 pf v b 47 w + 620 w 2.5 v v ol input 0.5 v v ol 50% 0.5 v v ol t en(d) t plz(d) 0.5 v v ol 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc notes: a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 1 mpps, pulsewidth = 500 ns 50 ns, z o = 50 w . b. c l includes instrumentation and fixture capacitance within 0,06 m of the d.u.t. figure 20. single-ended transceiver enable and disable timing measurements
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 24 post office box 655303 ? dallas, texas 75265 parameter measurement information de/re inv/non cde2 cde0 cde1 1.3 v open open 0 or 5 v 0 v test circuit voltage waveforms v id i ib+ v ib v ib i o i ib c l = 15 pf v o t plh v ib t phl 1.4 v 1 v 0.4 v v ib v id v o 0.4 v 50% v oh v ol 80% 20% t f t r 0 v 50 w 50 w solid line is inv/non at a high-level input. dashed line is inv/non at a low-level input. notes: a. note: all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse repetition rate (prr) = 10 mpps, pulsewidth = 50 ns 5 ns, z o = 50 w . b. c l includes instrumentation and fixture capacitance within 0,06 m of the d.u.t. figure 21. lvd receiver switching characteristic test circuit
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 25 post office box 655303 ? dallas, texas 75265 parameter measurement information t phl b de/re inv/non cde2 cde0 cde1 input gnd gnd open open gnd or v cc c l = 15 pf v o a output input 1.4 v t plh solid line is inv/non at a high-level input. dashed line is inv/non at a low-level input. i o 2 v 0.8 v 1.4 v t f t r 100% 80% 20% 0% v oh v ol notes: a. all input pulses are supplied by a generator having the following characteristics: t r or t f < 1 ns, pulse repetition rate (prr) = 10 mpps, pulsewidth = 50 ns 5 ns. b. c l includes instrumentation and fixture capacitance within 0,06 m of the d.u.t. figure 22. single-ended receiver timing test circuit
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 26 post office box 655303 ? dallas, texas 75265 application information u1 `lvdm976 cde0 diffsens 8.2 k w , 1/8 w, 5% 0.022 m f, 6 v, 10% u2 `lvdm976 cde0 u3 `lvdm976 cde0 figure 23. low-pass filter for connecting diffsens to cde0
SN75LVDM976, sn75lvdm977 9-channel dual-mode transceivers slls292b april 1998 revised january 2000 27 post office box 655303 ? dallas, texas 75265 mechanical information dgg (r-pdso-g**) plastic small-outline package 4040078 / f 12/97 48 pin shown 0,25 0,15 nom gage plane 6,00 6,20 8,30 7,90 0,75 0,50 seating plane 25 0,27 0,17 24 a 48 1 0,05 min 1,20 max m 0,08 0,10 0,50 0 8 56 14,10 13,90 48 dim a max a min pins ** 12,40 12,60 64 17,10 16,90 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customers are responsible for their applications using ti components. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

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